The present invention relates to a multilayer wiring board having a build-up structure comprising two or more wiring layers.
Multilayer wiring boards having a build-up structure are wiring boards that have been developed for the purpose of realizing high-density mounting of various electronic components. These multilayer wiring boards having a build-up structure are configured such that a plurality of wiring layers constituted by copper wires and resins and a plurality of resin base material layers constituted by resins and fiber bundles are alternately layered, and used for various digital devices and mobile devices.
First, a commonly used multilayer wiring board having a build-up structure will be described. FIG. 11 shows a partial cross section of a multilayer wiring board 100g (hereinafter, may be simply referred to as a “board”) having a build-up structure. In the board 100g, n (n is an integer of or more) wiring layers (C1 to Cn) and (n−1) resin base material layers [B1 to B(n−1)] are laminated in an alternately layered manner. Hereinafter, the wiring layers and the resin base material layers may be collectively referred to as “wiring layers C” and “resin base material layers B”, respectively.
The wiring layers C are constituted by a copper wire 101 and an insulating resin 103. The resin base material layers B are constituted by a fiber bundle 102 in the form of a woven or nonwoven fabric and the insulating resin 103 with which the fiber bundle 102 is impregnated. FIG. 11 schematically shows a state in which the fiber bundle 102 is impregnated with the resin 103 as the resin base material layers B. The layers are similarly shown also in the following drawings.
As the fiber bundle 102, glass fibers or aramid fibers are usually used. Furthermore, as the insulating resin 103, thermosetting resins such as epoxy resins, phenol resins, polyimide, or BT resin are used.
Typically, the wiring layers C and the resin base material layers B are formed by alternately layering fiber bundles that have been impregnated with an insulating resin and copper foils in which a wiring pattern has been formed, and curing the resin with application of pressure and heat in this state. The resin 103 constituting the wiring layers C is formed by causing a part of the resin with which the fiber bundles have been impregnated to enter gaps in the wiring pattern, at the time of application of pressure and heat.
Although not shown, the wiring layers C are electrically connected via a via-hole or through-hole formed through the resin base material layers B. The configuration of the above-described multilayer wiring board having a build-up structure is defined in detail in the standard set by Japan Electronics Packaging and Circuits Association “JPCA standard: Build-up Printed Wiring Boards (Terms and Definitions, Test Methods and Design examples)” (see Design examples 3 and 4 in page 2).
The resin base material layers B are divided into a base layer 104 functioning as a central layer in the multilayer structure and build-up layers 105 laminated above and below the base layer 104, in a laminating press process in manufacture of boards. Resin base materials constituting the base layer 104 and the build-up layers 105 may be the same or different. As resin base materials for the layers of the build-up layers 105, a single material is used in which the fiber bundle content is constant.
In a reflow soldering process, the board 100g in which electronic components are temporarily fixed on its front and rear mounting faces is placed on a reflow belt or reflow pallet, and the temperature is raised from room temperature to 220° C. or more to perform soldering and then lowered to room temperature. At that time, in the board 100g, the ratio of copper remaining (the ratio of the area of copper wires occupied in the entire area of the wiring layers C) differs between the wiring layers. Accordingly, the amount of thermal expansion differs between the wiring layers, and thus warpage occurs. The mechanism how warpage of the board occurs will be specifically described with reference to FIG. 12.
A board 100h shown in FIG. 12 has six wiring layers C1 to C6 arranged in that order from above and five resin base material layers that are arranged between the wiring layers, the resin base material layers comprising layers B1 and B2 (both are the build-up layers 105), B3 (the base layer 104), and B4 and B5 (both are the build-up layers 105) arranged in that order from above. The ratio of copper remaining in the wiring layers is 32%, 28%, 37%, 46%, 52%, and 54% in that order starting with the wiring layer C1. In this case, regarding the average of the ratio of copper remaining in layers (C1 to C3) situated above the base layer 104 (the resin base material layer B3) and that in layers (C4 to C6) situated therebelow, the average of the ratio of copper remaining in the layers situated below the base layer 104 is larger.
Comparison between the copper wire 101 and the resin 103 constituting the wiring layers C shows that the coefficient of linear expansion of the resin 103 is larger than that of the copper wire 101. Thus, wiring layers with a large ratio of copper remaining have a small amount of thermal expansion under temperature load. Thus, in the board 100h shown in FIG. 12, the amount of thermal expansion of the layers situated above the base layer 104 is large, and that of the layers situated therebelow is small. Accordingly, under temperature load, the board is warped to protrude upward.
If electronic components are mounted in a state where the board is still warped due to the reflow soldering process, the reliability in connection between the electronic components and the board is considerably lowered, which is a significant factor to deteriorate the quality of an electronic circuit in which the multilayer wiring board is installed.
In order to prevent warpage of a board in the reflow soldering process, the countermeasure shown in Japanese Laid-Open Patent Publication No. 2000-151015 is conventionally adopted. That is to say, as shown in FIG. 11, in order to minimize a difference in the amount of thermal expansion resulting from a difference between the ratios of copper remaining in the wiring layers C, a dummy pattern 108 is formed in the wiring layers C in addition to the original copper wire 101 constituting the electronic circuit, thereby making the ratio of copper remaining in the wiring layers C as uniform as possible.
However, in a board for small electronic devices in which electronic circuits are required to be mounted at high density, the area occupied by lands for mounting electronic components increases, and thus a sufficient space for disposing a dummy pattern cannot be secured. Furthermore, if components operating at high frequency are mounted on a board, arrangement of a dummy pattern is restricted because a dummy pattern leads to generation of noise. Thus, in the conventional countermeasure in which a dummy pattern is provided, there are limits in reducing warpage of the board.